module MFUNC_SUB3 ( /*AUTOARG*/
   // Outputs
   reg_MFUNC_SUB3_rd_data, params_other11, params_other12,
   params_other13, params_other14,
   // Inputs
   clk, rst_n, reg_MFUNC_SUB3_wr_en, sub_reg_addr, reg_wr_data,
   params_other15
   );
input         clk;
input         rst_n;
input         reg_MFUNC_SUB3_wr_en;
input  [11:0] sub_reg_addr;
input  [31:0] reg_wr_data;
output [31:0] reg_MFUNC_SUB3_rd_data;
output           params_other11;
output  [7:0]   params_other12;
output  [7:0]   params_other13;
output  [7:0]   params_other14;
input            params_other15;
/////////////////////////////////////////////////////
reg  [31:0]   reg_MFUNC_SUB3_rd_data;
reg           reg_000;
reg  [7:0]   reg_001;
reg  [7:0]   reg_002;
reg  [7:0]   reg_003;
reg           reg_004;
wire          wr_000_en;
wire          wr_001_en;
wire          wr_002_en;
wire          wr_003_en;
wire          wr_004_en;
assign          wr_000_en=(reg_MFUNC_SUB3_wr_en&&(sub_reg_addr==12'h000));
assign          wr_001_en=(reg_MFUNC_SUB3_wr_en&&(sub_reg_addr==12'h001));
assign          wr_002_en=(reg_MFUNC_SUB3_wr_en&&(sub_reg_addr==12'h002));
assign          wr_003_en=(reg_MFUNC_SUB3_wr_en&&(sub_reg_addr==12'h003));
assign          wr_004_en=(reg_MFUNC_SUB3_wr_en&&(sub_reg_addr==12'h004));
/////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_000<=1'b0;
    end
    else if (wr_000_en) begin
       reg_000<=reg_wr_data;
    end
end
assign  params_other11=reg_000;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_001<=8'h03;
    end
    else if (wr_001_en) begin
       reg_001<=reg_wr_data;
    end
end
assign  params_other12=reg_001;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_002<=8'h02;
    end
    else if (wr_002_en) begin
       reg_002<=reg_wr_data;
    end
end
assign  params_other13=reg_002;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_003<=8'h01;
    end
    else if (wr_003_en) begin
       reg_003<=reg_wr_data;
    end
end
assign  params_other14=reg_003;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_004<=1'd0;
    end
    else  begin
       reg_004<=params_other15;
    end
end
always @( * )
begin
    case(sub_reg_addr) 
    12'h000 : reg_MFUNC_SUB3_rd_data=reg_000;
    12'h001 : reg_MFUNC_SUB3_rd_data=reg_001;
    12'h002 : reg_MFUNC_SUB3_rd_data=reg_002;
    12'h003 : reg_MFUNC_SUB3_rd_data=reg_003;
    12'h004 : reg_MFUNC_SUB3_rd_data=reg_004;
    default : reg_MFUNC_SUB3_rd_data=32'h5a5a_a5a5;
    endcase
end
endmodule
